题解 | #并串转换#
并串转换
https://www.nowcoder.com/practice/296e1060c1734cf0a450ea58dd09d36c
`timescale 1ns/1ns module huawei5( input wire clk , input wire rst , input wire [3:0]d , output reg valid_in , output wire dout ); //*************code***********// reg [3:0] d1; reg [1:0] cnt; always@(posedge clk or negedge rst) if(!rst) d1<=4'b0; else if(cnt==2'd3) d1<=d; //观察波形cnt==3的下一拍才数据才进来 always@(posedge clk or negedge rst) if(!rst) cnt<=2'b0; else if(cnt==2'd3) cnt<=2'd0; else cnt <= cnt + 1'd1; always@(posedge clk or negedge rst) if(!rst) valid_in<=1'b0; else if(cnt==2'd3) valid_in<=1'b1; else valid_in<=1'b0; //assign valid_in = cnt==2'd3; assign dout = d1[3-cnt]; /*always@(posedge clk or negedge rst) if(!rst) dout<=4'b0; else if(cnt==2'd0) dout<=d1[3]; else if(cnt==2'd1) dout<=d1[2]; else if(cnt==2'd2) dout<=d1[1]; else if(cnt==2'd3) dout<=d1[0]; */ //*************code***********// endmodule
