题解 | #多bit MUX同步器#
多bit MUX同步器
https://www.nowcoder.com/practice/30e355a04a454e16811112cb82af591e
dataout
`timescale 1ns/1ns
module mux(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_d_clka;
reg en_d_clka;
reg en_d_clkb_d1;
reg en_d_clkb_d2;
//save data in clka domain
always@(posedge clk_a or negedge arstn)
if(!arstn) data_d_clka <= 1'b0;
else if(data_d_clka ^data_in) data_d_clka <= data_in;
//save en in clka domain
always@(posedge clk_a or negedge arstn)
if(!arstn) en_d_clka <= 1'b0;
else if(en_d_clka ^data_en) en_d_clka <= data_en;
//en cross-domain
always@(posedge clk_b or negedge brstn)
if(!brstn) en_d_clkb_d1 <= 1'b0;
else if(en_d_clkb_d1 ^en_d_clka) en_d_clkb_d1 <= en_d_clka;
always@(posedge clk_b or negedge brstn)
if(!brstn) en_d_clkb_d2 <= 1'b0;
else if(en_d_clkb_d2 ^en_d_clkb_d1) en_d_clkb_d2 <= en_d_clkb_d1;
always@(posedge clk_b or negedge brstn) begin
if(!brstn) dataout <= 4'b0;
else if(en_d_clkb_d2) dataout <= data_d_clka;
end
endmodule
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