题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
    reg [1:0] cstate,nstate;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cstate <= 2'd0;
        end
        else begin
            cstate <= nstate;
        end
    end
    always@(*) begin
        case(cstate)
            2'b00: nstate = C?2'b01:cstate;
            2'b01: nstate = C?cstate:2'b11;
            2'b10: nstate = C?cstate:2'b00;
            2'b11: nstate = C?2'b10:cstate;
            default: nstate = 2'b00;
        endcase
    end
    assign Y = (cstate==2'b11) | ((cstate==2'b10) & C);
endmodule