题解 | #根据状态转移表实现时序电路#
根据状态转移表实现时序电路
https://www.nowcoder.com/practice/455c911bee0741bf8544a75d958425f7
`timescale 1ns/1ns
module seq_circuit(
input A ,
input clk ,
input rst_n,
output wire Y
);
parameter STATE0=2'b00;
parameter STATE1=2'b01;
parameter STATE2=2'b10;
parameter STATE3=2'b11;
reg [1:0]state,next_state;
always@(*)begin
case(state)
STATE0:next_state=A?STATE3:STATE1;
STATE1:next_state=A?STATE0:STATE2;
STATE2:next_state=A?STATE1:STATE3;
STATE3:next_state=A?STATE2:STATE0;
default:next_state=STATE0;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
state<=STATE0;
end
else begin
state<=next_state;
end
end
assign Y=(state==STATE3);
endmodule
module seq_circuit(
input A ,
input clk ,
input rst_n,
output wire Y
);
parameter STATE0=2'b00;
parameter STATE1=2'b01;
parameter STATE2=2'b10;
parameter STATE3=2'b11;
reg [1:0]state,next_state;
always@(*)begin
case(state)
STATE0:next_state=A?STATE3:STATE1;
STATE1:next_state=A?STATE0:STATE2;
STATE2:next_state=A?STATE1:STATE3;
STATE3:next_state=A?STATE2:STATE0;
default:next_state=STATE0;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
state<=STATE0;
end
else begin
state<=next_state;
end
end
assign Y=(state==STATE3);
endmodule