题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    
    
    reg    [15:0]    data_out_temp;
    
    reg    [1:0]     data_in_cnt;
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_in_cnt <= 2'b0;
        else if(valid_in)
            begin
                if(data_in_cnt == 2'd1)
                    data_in_cnt <= 2'b0;
                else
                    data_in_cnt <= data_in_cnt + 1'b1;
            end
        else
            data_in_cnt <= data_in_cnt;
    end
    
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            data_out_temp <= 16'b0;
        else if(valid_in)
            data_out_temp <= {data_out_temp[7:0] , data_in};
        else
            data_out_temp <= data_out_temp;
    end
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            begin
                data_out <= 16'b0;
                valid_out <= 1'b0;
            end
        else if(valid_in)    //以后此处还是要加上这个判断，不然还是会报错，他会在非有效段进行下面的运算，从而导致出错
            begin
                if(data_in_cnt == 2'd1)
                    begin
                        data_out <= {data_out_temp[7:0] , data_in};
                        valid_out <= 1'b1;
                    end
                else
                    begin
                        data_out <= data_out;
                        valid_out <= 1'b0;
                    end
            end
        else
            begin
                data_out <= data_out;
                valid_out <= 1'b0;
            end
    end
    
    
endmodule