题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
    input wire clk  ,
    input wire rst  ,
    input wire d1 ,
    input wire d2 ,
    input wire d3 ,
    
    output reg out1,
    output reg [1:0]out2
);
//*************code***********//
parameter IDEL    =    7'b0000001;
parameter HALF     =    7'b0000010;
parameter ONE     =    7'b0000100;
parameter ONE_HALF = 7'b0001000;
parameter TWO     =    7'b0010000;
parameter TWO_HALF = 7'b0100000;
parameter THREE =    7'b1000000;
reg [6:0] state;
//state
always @(posedge clk or negedge rst) begin  
    if(~rst) begin
        state <= 0;
    end 
    else 
        case (state)
            IDEL: 
            if({d1,d2,d3}==3'b100)begin state <= HALF; end
            else if ({d1,d2,d3}==3'b010) begin state <= ONE; end
            else if ({d1,d2,d3}==3'b001) begin state <= TWO; end
            HALF: 
            if({d1,d2,d3}==3'b100)begin state <= ONE; end
            else if ({d1,d2,d3}==3'b010) begin state <= ONE_HALF; end
            else if ({d1,d2,d3}==3'b001) begin state <= TWO_HALF; end
            ONE: 
            if({d1,d2,d3}==3'b100)begin state <= ONE_HALF; end
            else if ({d1,d2,d3}==3'b010) begin state <= TWO; end
            else if ({d1,d2,d3}==3'b001) begin state <= THREE; end
                // ONE_HALF: state <= IDEL;
                // TWO: state <= IDEL;
                // TWO_HALF: state <= IDEL;
                // THREE: state <= IDEL;
                default : state <= IDEL;
        endcase
end        
//out1
always @(posedge clk or negedge rst) begin  
    if(~rst) begin
        out1  <= 0;
    end 
    else if(state == ONE_HALF||state == TWO||state == TWO_HALF||state == THREE)begin
        out1  <= 1;
    end
    else begin
        out1  <= 0;
    end
end
//out2
always @(posedge clk or negedge rst) begin  
    if(~rst) begin
        out2  <= 0;
    end 
    else if(state == TWO)begin
        out2  <= 1;
    end
    else if(state == TWO_HALF)begin
        out2  <= 2;
    end
    else if(state == THREE)begin
        out2  <= 3;
    end    
    else begin
        out2  <= 0;
    end
end

//*************code***********//
endmodule