题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match );

reg [8:0] vector;

always @(posedge clk or negedge rst_n) begin
    if (! rst_n) begin
        vector <= 8'd0;
    end
    else vector[8:0] <= {vector[7:0], a};
end

always @(posedge clk or negedge rst_n) begin
    if (! rst_n) begin
        match <= 0;
    end
    else if (vector[8:6] == 3'b011 && vector[2:0] == 3'b110)
        match <= 'b1;
    else match <= 0;
end

endmodule