题解 | #自动贩售机2#

https://www.nowcoder.com/practice/298dec1c3dce45c881f3e53e02558828

`timescale 1ns/1ns

module seller2(input wire clk,
input wire rst,
input wire d1,
input wire d2,
input wire sel,
output reg out1,
output reg out2,
output reg out3);
//*************code***********//

//d1 0.5 d2 1 sel????????????????????????1?????????????????????2

localparam s0 = 4'b0000;
localparam s1 = 4'b0001;
localparam s2 = 4'b0010;
localparam s3 = 4'b0100;
localparam s4 = 4'b1000;

reg [3:0] cs,ns;
reg [1:0] din;
//题目里并没有要求二段式或者三段式，但是必须时三段式才能和预设的波形一致，sb吧
reg out1_reg,out2_reg,out3_reg;

always @(posedge clk or negedge rst) begin
if (!rst) din <= 'b0;
else din <= {d2,d1};
end

always @(posedge clk or negedge rst) begin
if (!rst) begin
out1 <= 0;
out2 <= 0;
out3 <= 0;
end
else begin
out1 <= out1_reg;
out2 <= out2_reg;
out3 <= out3_reg;
end
end


always @(posedge clk or negedge rst) begin
if (!rst) cs <= 'b0;
else cs <= ns;
end

always @(*) begin
if (!sel) begin
case (cs)
s0:begin
if (din == 2'b00) begin
ns = s0;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s1;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
end
s1:begin
if (din == 2'b00) begin
ns = s1;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s0;
out1_reg = 1;
out2_reg = 0;
out3_reg = 0;
end
end
s2:begin
if (din == 2'b00) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s0;
out1_reg = 1;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s0;
out1_reg = 1;
out2_reg = 0;
out3_reg = 1;
end
end
default: begin
ns = s0;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
endcase
end else begin
case(cs)
s0:begin
if (din == 2'b00) begin
ns = s0;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s1;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
end
s1:begin
if (din == 2'b00) begin
ns = s1;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s3;
out1_reg = 1;
out2_reg = 0;
out3_reg = 0;
end
end
s2:begin
if (din == 2'b00) begin
ns = s2;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s3;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s4;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
end
s3:begin
if (din == 2'b00) begin
ns = s3;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s4;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s0;
out1_reg = 0;
out2_reg = 1;
out3_reg = 0;
end
end
s4:begin
if (din == 2'b00) begin
ns = s4;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
else if (din == 2'b01) begin
ns = s0;
out1_reg = 0;
out2_reg = 1;
out3_reg = 0;
end
else if (din == 2'b10) begin
ns = s0;
out1_reg = 0;
out2_reg = 1;
out3_reg = 1;
end
end
default:begin
ns = s0;
out1_reg = 0;
out2_reg = 0;
out3_reg = 0;
end
endcase
end
end



//*************code***********//
endmodule