题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input data,
    output reg match,
    output reg not_match
    );
    reg [3:0] curr_state;
    reg [3:0] next_state;
    always @ (posedge clk, negedge rst_n)begin
        if (~rst_n)begin
        curr_state<=4'd0;
        end
        else begin
            curr_state<=next_state;
        end
    end
    
    always @ (*)begin
        case(curr_state)
            4'd0:next_state=(data==1'b1)?4'd7:4'd1;
            
            4'd1:next_state=(data==1'b1)?4'd2:4'd8;
            4'd2:next_state=(data==1'b1)?4'd3:4'd9;
            4'd3:next_state=(data==1'b1)?4'd4:4'd10;
            4'd4:next_state=(data==1'b1)?4'd11:4'd5;
            4'd5:next_state=(data==1'b1)?4'd12:4'd6;
            
            4'd6:next_state=(data==1'b1)?4'd0:4'd1;
            
            4'd7:next_state=4'd8;
            4'd8:next_state=4'd9;
            4'd9:next_state=4'd10;
            4'd10:next_state=4'd11;
            4'd11:next_state=4'd12;
            
            4'd12:next_state=(data==1'b1)?4'd7:4'd1;
            default:next_state=4'd0;
        endcase
    end
    always @ (posedge clk, negedge rst_n)begin
        if (~rst_n)begin
            match <= 1'b0;
            not_match<= 1'b0;
        end
        else begin
            match<=(next_state==4'd6);
            not_match<= (next_state==4'd12);
        end
    end    

endmodule