题解 | #根据状态转移图实现时序电路#
根据状态转移图实现时序电路
http://www.nowcoder.com/practice/e405fe8975e844c3ab843d72f168f9f4
`timescale 1ns/1ns
module seq_circuit( input C , input clk , input rst_n,
output wire Y
);
reg [1:0]state;
always@(posedge clk,negedge rst_n) if(!rst_n) state <= 2'b00; else case(state) 2'b00:state <= C?2'b01:2'b00; 2'b01:state <= C?2'b01:2'b11; 2'b10:state <= C?2'b10:2'b00; 2'b11:state <= C?2'b10:2'b11; default:; endcase assign Y = (state == 2'b11) | (state == 2'b10&C);
endmodule

