【开卷】第25期 艾为2022数字芯片设计笔试题
艾为2022数字芯片设计笔试题
笔试日期2021.09.02
1.已知八进制数:- (362) 8,求它的
十进制数是:
二进制原码是:
反码是:
补码是:
A. A+BC
B. A+C
C.AB+BC
D.A+B+C
5.十进制数46的格雷码是哪个?( )
A.100011
B.101110
C.111001
D.111110
6. X表示任意项,如图所示卡诺图,求化简后的逻辑表达式:
A.NAND
B.NOR
C.AND
D.XOR
8.如图所示逻辑电路,其中FA为全加器,LG为单个逻辑门,若F=0时,输出为X3X2X1X0+Y3Y2Y1Y0;F=1时,输出为X3X2X1X0-Y3Y2Y1Y0,则LG应为:( )
A.OR
B.NOR
C.NAND
D.XOR
9.如图所示电路的CLK为20kHz,状态图数字排列为Q3Q2Q1Q0,若初始状态为0000,则该电路的状态图为哪个?( )
A.
B.
C.
D.
A.6
B.7
C.8
D.9
11. 如图所示电路,LG为哪种逻辑门电路,才可以得到如表的实验结果?( )
A.AND
B.NOR
C.NAND
D.XOR
A.电源开启后,LED亮,按下S1放开后,LED暗,之后再按下S1时,LED没有变化
B.电源开启后,LED亮,按下S1放开后,LED开始闪烁,再次按下S1则停止闪烁,LED灭,重复以上动作
C.电源开启后,LED暗,按住S1按钮时,LED亮,放开S1则LED灭,重复以上动作
D.电源开启后,LED暗,按住S1按钮时,LED闪烁,放开S1则LED灭,之后再按S1时,LED没有变化
A.输出频率100kHz,正脉冲宽度为2us
B.输出频率100kHz,正脉冲宽度为5us
C.输出频率500kHz,正脉冲宽度为2us
D.输出频率500kHz,正脉冲宽度为8us
简答
14.什么是亚稳态?如何防止亚稳态传播或减少亚稳态概率?
15.请用verilog/vhdl实现5分频电路,占空比50%
16.用FSM实现一个序列检测模块,a为输入端,b为输出端,如果a连续输入为1101,则b输出为1,否则为0。例如:
a: 0001100110110100100110
b: 0000000000100100000000
请画出状态转移图并写出Verilog代码。
17.翻译以下段落,并根据描述画出I2C接口的start和stop时序:
The I2C bus employs two signals, SDA(data)and SCL (clock), to communicate between integrated circuits in a system.Thebus transfers data serially, one bit at a time. The 8-bit address anddatabytes are transferred with the most-significant bit (MSB) first. Inaddition, each byte transferred on the bus is acknowledged by the receivingdevice withan acknowledge bit. Each transfer operation begins with the masterdevicedriving a start condition on the bus and ends with the master devicedriving astop condition on the bus. The bus uses transitions on the data pin(SDA) whilethe clock is at logic high to indicate start and stop conditions. Ahigh-to-lowtransition on the SDA signal indicates a start, and a low-to-hightransitionindicates a stop. Normal data-bit transitions must occur within thelow time ofthe clock period.
本文首发于微信公众号【 数字IC打工人】,点击绿色字体,交个朋友呀~
收录各大芯片公司笔试真题