题解 | #输入序列不连续的序列检测#
输入序列不连续的序列检测
http://www.nowcoder.com/practice/f96d0e94ec604592b502b0f1800ed8aa
解法1，更统一的代码风格:
match <= data_valid && ({seq[2:0], data} == t_seq);
这样判断和时钟分频等代码风格统一：
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
parameter t_seq = 4'b0110;
reg [3:0] seq;
//移位模块
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
seq <= 4'h0;
//cnt <= 4'h0;
end
else if(data_valid) begin
seq <= {seq[2:0], data};
//cnt <= cnt + 'd1;
end
else
seq <= seq;
end
// always @ (*) begin
// match = (seq == 4'b0110) &&;
// end
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
match <= 1'b0;
end
else
match <= data_valid && ({seq[2:0], data} == t_seq);
end
// always @ (posedge clk, negedge rst_n) begin
// if(!rst_n) begin
// match <= 1'b0;
// end
// else if(data_valid && (seq[2:0]==3'b011) && (!data)) begin
// match <= 1'b1;
// end
// else
// match <= 1'b0;
// end
endmodule
解法2：
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
parameter t_seq = 4'b0110;
reg [3:0] seq;
//移位模块
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
seq <= 4'h0;
//cnt <= 4'h0;
end
else if(data_valid) begin
seq <= {seq[2:0], data};
//cnt <= cnt + 'd1;
end
else
seq <= seq;
end
// always @ (*) begin
// match = (seq == 4'b0110) &&;
// end
always @ (posedge clk, negedge rst_n) begin
if(!rst_n) begin
match <= 1'b0;
end
else if(data_valid && (seq[2:0]==3'b011) && (!data)) begin
match <= 1'b1;
end
else
match <= 1'b0;
end
endmodule