题解 | #状态机与时钟分频#

三段状态机

//**code//

timescale 1ns/1ns
module huawei7(
input wire clk  ,
input wire rst  ,
output reg clk_out

); reg [3:0] state ,next_state;

//独热编码
parameter s0 = 4'b0001;
parameter s1 = 4'b0010;
parameter s2 = 4'b0100;
parameter s3 = 4'b1000;

//状态跳转
always @ (posedge clk or negedge rst)begin
    if(!rst)
        state <= s0;
    else
        state <= next_state;
end
//跳转
always @ (*)begin
    case(state)
        s0 : next_state <= s1;
        s1 : next_state <= s2;
        s2 : next_state <= s3;
        s3 : next_state <= s0;
        default : next_state <= s0;
    endcase
end

//输出
always @ (posedge clk or negedge rst)begin
    if(!rst)
        clk_out <= 1'b0;
    else if(next_state == s1) //看时序图在第一个时钟上升沿进行赋值此时状态为s1
        clk_out <= 1'b1;
    else
        clk_out <= 1'b0;
end
endmodule

//**code//