题解 | #根据RTL图编写Verilog程序#
根据RTL图编写Verilog程序
http://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns
module RTL(
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg data_in_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
data_in_r <= 1'd0;
else
data_in_r <= data_in;
end
wire data_r;
assign data_r = data_in & (~data_in_r);
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
data_out <= 1'b0;
else
data_out <= data_r;
end
endmodule
module RTL(
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg data_in_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
data_in_r <= 1'd0;
else
data_in_r <= data_in;
end
wire data_r;
assign data_r = data_in & (~data_in_r);
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
data_out <= 1'b0;
else
data_out <= data_r;
end
endmodule
