题解 | #数据串转并电路#

````timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
    reg [2:0]cnt;
    reg [5:0]data_bb;
    always@(posedge clk or negedge rst_n)
        if(!rst_n) begin 
           ready_a <= 1'b0;
           valid_b <= 1'b0;
            data_bb <= 6'b0;
            data_b <= 6'b0;
            cnt <= 3'b0;  end
    else begin
        ready_a <= 1'b1;
        if(valid_a) begin
            data_bb <= {data_a, data_bb[5:1]};
            if(cnt == 3'd5)begin 
                cnt <= 3'd0;
                valid_b <= 1'b1;
                data_b <= {data_a, data_bb[5:1]};
            end
            else begin
                cnt <= cnt + 1'd1;
                valid_b <= 1'b0; end
        end
        else begin 
            data_bb <= data_bb;
            valid_b <= valid_b; end
    end
endmodule