题解 | #脉冲同步器（快到慢）#
脉冲同步器（快到慢）
http://www.nowcoder.com/practice/9f7c92635b5f49579e8e38fd8c8450d7
上图中最左端的数据选择器和寄存器，组成了快时钟域下的翻转电路；中间的两个寄存器是两级同步器；最后一个寄存器和异或门组成边沿检测电路。
根据电路设计，Verilog代码描述如下：
reg Q_sig_a; always @(posedge clka or negedge rst_n) begin if(~rst_n) begin Q_sig_a <= 'd0; end else if(sig_a)begin Q_sig_a <= ~Q_sig_a; end else if(~sig_a)begin Q_sig_a <= Q_sig_a; end end reg Q_buff0; reg Q_buff1; always @(posedge clkb or negedge rst_n) begin if(~rst_n) begin Q_buff0 <= 'd0; Q_buff1 <= 'd0; end else begin Q_buff0 <= Q_sig_a; Q_buff1 <= Q_buff0; end end reg Q_slow; always @(posedge clkb or negedge rst_n) begin if(~rst_n) begin Q_slow <= 'd0; end else begin Q_slow <= Q_buff1; end end assign sig_b = Q_buff1 ^ Q_slow;
3 仿真结果
参考答案
`timescale 100ps/100ps module pulse_detect( input clka , input clkb , input rst_n , input sig_a , output sig_b ); reg Q_sig_a; always @(posedge clka or negedge rst_n) begin if(~rst_n) begin Q_sig_a <= 'd0; end else if(sig_a)begin Q_sig_a <= ~Q_sig_a; end else if(~sig_a)begin Q_sig_a <= Q_sig_a; end end reg Q_buff0; reg Q_buff1; always @(posedge clkb or negedge rst_n) begin if(~rst_n) begin Q_buff0 <= 'd0; Q_buff1 <= 'd0; end else begin Q_buff0 <= Q_sig_a; Q_buff1 <= Q_buff0; end end reg Q_slow; always @(posedge clkb or negedge rst_n) begin if(~rst_n) begin Q_slow <= 'd0; end else begin Q_slow <= Q_buff1; end end assign sig_b = Q_buff1 ^ Q_slow; endmodule
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