题解 | #数据累加输出#

//data_out不需要中介变量赋值，虽然波形图里的data_out在ready_a拉高之后数据也没有发生变化，似乎比较矛盾

`timescale 1ns/1ns

module valid_ready( input clk ,
input rst_n , input [7:0] data_in , input valid_a , input ready_b ,

output		 		ready_a		,
output	reg			valid_b		,
output  reg [9:0] 	data_out

);

//计数输入的数值，四个数据
reg [1:0] cnt;
always@(posedge clk,negedge rst_n)begin
    if(!rst_n)begin
       cnt<=0;
       data_out<=0;
    end
    else if(valid_a&&!cnt&&ready_a)begin //cnt计数从3到0的时候需要清除data_out上一轮数据
            cnt<='d1;
            data_out<=data_in;
    end
    else if(valid_a&&ready_a)begin
            cnt<=cnt+'d1;
            data_out<=data_in+data_out;
            end
    else begin end
end
  
assign ready_a = valid_b?ready_b:1'd1;//ready_a在valid_b拉高时候，取值根据read_b，valid_b拉低时候时候为高电平 

always@(posedge clk,negedge rst_n)begin
    if(!rst_n)
    valid_b<=0; 
    else if(cnt=='d3&&valid_a)
        valid_b<='d1;
    else if(ready_b&&valid_b)
        valid_b<=0;
    else if(!ready_b) 
        valid_b<=valid_b;
    else begin end
end

endmodule