Synopsys（新思科技）校招开启啦！

Synopsys 新思科技2020校园招聘！

v 关于我们

Synopsys（Synopsys, Inc.，纳斯达克股票市场代码： SNPS）致力于创新改变世界，在芯片（Silicon）到软件（Software）的众多领域，Synopsys始终引领和参与全球各个科技公司的紧密合作，共同开发人们所依赖的电子产品和软件应用。Synopsys 是全球排名第一的电子设计自动化（EDA）供应商和全球排名第一的半导体接口IP供应商，同时也是软件质量和安全解决方案的全球领导者, 位列世界第15大软件公司，并荣选美国标准普尔500指数成分股龙头企业。Synopsys总部位于美国硅谷，成立于1986年，目前拥有13400多名员工，分布在全球100多个分支机构。2018年财年营业额逾31亿美元，拥有3100多项已批准专利。作为半导体、人工智能、汽车电子及软件安全等产业的核心技术提供商与驱动者，Synopsys的技术一直深刻影响着当前全球五大新兴科技创新应用：智能汽车、物联网、人工智能、云计算和信息安全。

自1995年进入中国市场以来，Synopsys已在北京、上海、深圳、西安、武汉、南京、厦门、***、澳门九大城市设立机构，员工人数已超过1300人，建立了完善的技术研发和支持服务体系，秉持“加速创新、推动产业、成就客户”的方针，与产业及合作伙伴携手共进、共同发展，成为中国半导体产业快速发展的优秀伙伴和坚实支撑。

v 加入我们

投递邮箱: lijian@synopsys.com
如果对我们以下职位感兴趣，请将简历以”姓名_学校_专业_地点_期望职位”的格式附在邮件中发送到lijian@synopsys.com，收到后我们会及时与你联系。

Position: (Location: Wuhan)

1\IP数字工程师

2\模拟混合信号设计工程师

3\版图设计工程师

4\CAD软件工程师

Position: (Location: Shanghai)

5\ Software Engineer(软件工程师)for EDA tools

6\IP数字验证工程师

7\IP数字设计工程师

1\数字工程师（武汉）

基本要求
- 微电子、电子工程、通信或相关专业研究生
Typically requires fresh master/PHD graduate with the major of microelectronics, telecommunication,

Electrical/Electronic Engineering, or relevance
- 熟悉数字设计的基本流程，熟练使用Verilog语言对数字电路进行设计或SystemVerilog进行验证
Familiar with basic digital design flow, experience with Verilog language for digital design or SystemVerilog

for verification
- 有使用过脚本语言，如TCL, Perl, Python等
Experience with TCL, Perl, Python, or other scripting languages

岗位关键词
- 从事的相关产品是接口控制器 (Interface controller) / 高速DDR PHY /静态存储器/处理器 (Processor) 等
The related products are Interface controller, High Speed DDR PHY, Static memory，Processor etc.
- 使用先进设计工艺（如5nm/7nm/10nm），从事数字设计，UVM验证，以及业内领先的开发流程相关

工作，如Timing，DFT, Firmware等相关工作
Work on Digital Design, UVM Verification, and state-of-the-art implementation flow development

including Timing, DFT and Firmware tasks with advanced technology (5nm/7nm/10nm).

2\模拟混合信号设计工程师（武汉）
基本要求：
- 电子工程或相关专业硕士
Master’s in EE and related fields
- 熟练使用电路设计工具，版图设计工具以及SPICE仿真工具
Experience with tools for schematic entry, IC layout and SPICE simulation
- 熟练使用Verilog-A语言对模拟电路进行行为级建模和仿真
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
- 有使用TCL，Perl，C，Python，MATLAB或其他脚本语言的经验
Experience with TCL, perl, C, python, MATLAB, or other scripting languages
- 有一定听说写能力
Writing and reading English can meet basic daily working requirements

岗位关键词：
- 使用最先进的工艺（如7nm/10nm）开发创新型模拟与混合集成电路
Design innovative analog and mixed-signal integrated circuits based on advanced technology (like 7nm/10nm)
- 与全球具有不同技术背景的模拟/数字电路设计工程师协同工作
Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds
- 从事与模拟混合信号相关的IP设计
involve related to analog design and mixed signal IP design
- 基于CMOS器件的电路设计，开发随机存储器及版图
Circuit Design, SRAM, Layout

3\版图设计工程师 （武汉）
基本要求：
- 学士及学士以上学历 （微电子，电子信息，或者自动化专业优先考虑）
Bachelor or above degree in Microelectronics, electronics, automation related major is preferred
- 有版图设计经验优先考虑
Layout relevant project experience is prior
- 英文通过四级，有一定听说写能力
Language proficiency over level 4 and listening, writing and reading can meet basic daily working requirements
- 良好的合作和沟通能力
Good team player and skillful communication

岗位关键词：
- 使用先进工艺（如7nm/10nm）根据电路设计完成版图设计。验证版图设计的DRC/LVS，确保版图设计正确性
According schematic to custom design layout with advanced process node (Like 7nm/10nm), verify layout design with DRC/LVS deck
- 与全球具有不同技术背景工程师协同工作
Work with a cross functional design team from a wide variety of backgrounds

4\CAD软件工程师 （武汉）

Responsibilities:
In this role the candidate will be responsible for:
1. Designing, developing, troubleshooting, or debugging software tools and flows for the development of integrated circuits.
2. Determining hardware compatibility and/or influencing hardware design.
3. Supporting a global design team with debugging CAD issues, interfacing with foundries, configuring the CAD environment and design flows to support the design of integrated circuits.
4. Developing routines and utility programs to aid in the design of integrated circuits.
5. Receiving general instructions on routine work, detailed instructions on new assignments; implementations and solutions are reviewed for accuracy and overall adequacy.
6.Building productive internal/external working relationships

Specific Requirements:
We need people who are able to work in multi-functional teams, are capable of understanding requirements and come up with creative solutions, are reliable in following existing procedures but have a critical opinion regarding what they are doing and can tradeoff the optimal with the best on a daily basis.

Candidates should have:
1. University degree in Physics or Electrical/Computers/Materials Engineering
2. Fluency in the English language
3. Experience on development of software and/or hardware projects, familiarity with software coding and scripting languages, and a strong background in data structures and algorithms
4. Strong desires to learn and explore new technologies and demonstrate good analysis and problem-solving skills
5. Circuit theory knowledge
6. Ability to exercise judgment within defined procedures and practices to determine appropriate action
7. Team player

Favored Requirements
1. Previous working experience in VLSI CAD domain
2. Experience in physical layout design, Extraction and Simulation
3. Expert Programming skills in at least one language and good knowledge of hardware integrated circuits

5\ Software Engineer(软件工程师)for EDA tools（Shanghai）

Responsible for designing, developing and debugging EDA software. This role will focus on data hierarchy, concurrent algorithms, and distributed processing areas to maintain and improve compression, performance, and scalability.

Requirements:
• M.S.or Ph.D. in Computer Science, Engineering, or Physical Sciences .(欢迎应届毕业生)
• Familiar with software development and testing methodologies
• Proficient in C/C++, experience in developing complex programs is a plus.
• Good problem solving skills and the ability to communicate in English.

6\IP数字验证工程师（Shanghai）

Responsibility:
This position is for leading edge IP verification
Study existing UVM test environment and make improvements
Define verification spec based on standard specifications
Write and debug test cases to verify RTL design at IP level
Collect and improve code and functional coverage
Maintain regression tests and debug test failures
Work with VIP teams for VIP issues

Qualification:
Be familiar with SystemVerilog, knowledge in UVM is a plus
Be fluent in English, both speaking and writing
Knowledge in software programming, e.g. C/C++, Python, is a plus
Knowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plus
Knowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plus
Has strong desire to learn and explore new technologies
Demonstrates good attitude in team work

7\IP数字设计工程师（Shanghai）

Responsibility:
This position is for leading edge IP design.
Study standard specifications published by JEDEC
Define micro architecture at block level based on IP architecture
Work on RTL design based on predefined coding style, SVA is also included
Clean RTL check violations in lint, CDC, DFT and synthesis
Run block level test to speed up IP verification
Work with verification to debug and fix RTL issues
Check synthesis timing and improve RTL design if required

Qualification:
Be familiar with RTL design
Be fluent in English, both speaking and writing
Knowledge in software programming, e.g. C/C++, Python, is a plus
Knowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plus
Knowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plus
Has strong desire to learn and explore new technologies
Demonstrates good attitude in team work