RTL `timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg dff1; always @ (posedge clk, negedge rst_n) begin if(!rst_n) dff1 <= 1'b0; else dff1 <= data_in; end always @ (posedge clk, negedge rst_n) begin if(!rst_n) data_out <= 1'b0; else data_out &l...