题解 | 并串转换

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

	reg [1:0] cnt;
	reg [3:0] data;
	reg flag;
	always@(posedge clk or negedge rst)begin
		if(!rst)begin
			cnt <= 'd0;
		end
		else begin
			cnt <= cnt + 1'b1;
		end
	end

	always@(posedge clk or negedge rst)begin
		if(!rst) begin
			data <= 'd0;
		end
		else if(cnt == 2'd3) begin
			data <= d;
		end
		else begin
			data <= {data[2:0],1'b0};
		end
	end
	always@(posedge clk or negedge rst)begin
		if(!rst) begin
			flag<=1'b0;
		end
		else if(cnt == 2'd3) begin
			flag<=1'b1;
		end
		else begin
			flag<=1'b0;
		end
	end


	assign valid_in = flag;
	assign dout = data[3];
	
endmodule