题解 | 信号发生器

`timescale 1ns / 1ns
module signal_generator (
    input clk,
    input rst_n,
    input [1:0] wave_choise,
    output reg [4:0] wave
);
    reg [4:0] cnt;
    reg [1:0] wave_choise_reg;
    reg flag;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wave_choise_reg <= 0;
        end else begin
            wave_choise_reg <= wave_choise;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 0;
        end else if (wave_choise != wave_choise_reg || cnt == 'd19) begin
            cnt <= 0;
        end else begin
            cnt <= cnt + 1;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            flag <= 0;
        end else if (wave_choise == 'd2 && wave == 'd1) begin
            flag <= 1;
        end else if (wave == 'd19) begin
            flag <= 0;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wave <= 0;
        end else begin
            case (wave_choise)
                'd0: begin
                    if (cnt == 'd9) begin
                        wave <= 20;
                    end else if (cnt == 'd19) begin
                        wave <= 0;
                    end
                end
                'd1: begin
                    if (wave == 'd20) begin
                        wave <= 0;
                    end else begin
                        wave <= wave + 1;
                    end
                end
                'd2: begin
                    if (!flag) begin
                        wave <= wave - 1;
                    end else if (flag) begin
                        wave <= wave + 1;
                    end
                end
                default: wave <= 0;
            endcase
        end
    end

endmodule

题目太模糊了，我也是参考别人的写出来的也可以用条件运算符减少一下代码行数：

`timescale 1ns / 1ns
module signal_generator (
    input clk,
    input rst_n,
    input [1:0] wave_choise,
    output reg [4:0] wave
);
    reg [4:0] cnt;
    reg [1:0] wave_choise_reg;
    reg flag;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wave_choise_reg <= 0;
        end else begin
            wave_choise_reg <= wave_choise;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 0;
        end else if (wave_choise != wave_choise_reg || cnt == 'd19) begin
            cnt <= 0;
        end else begin
            cnt <= cnt + 1;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            flag <= 0;
        end else if (wave_choise == 'd2 && wave == 'd1) begin
            flag <= 1;
        end else if (wave == 'd19) begin
            flag <= 0;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wave <= 0;
        end else begin
            case (wave_choise)
                'd0: wave <= (cnt == 'd9) ? 20 : ((cnt == 'd19) ? 0 : wave);
                'd1: wave <= (wave == 'd20) ? 0 : wave + 1;
                'd2: wave <= flag ? wave + 1 : wave - 1;
                default: wave <= 0;
            endcase
        end
    end

endmodule

矩形波生成时注意在第10个周期判断，更新第11个周期的wave值；

锯齿波和三角波等缓变波强烈依赖wave自身的值，可以得出存在反馈控制，同样观察波形我们看到，当wave=20时下一周期会跳变到0；

在三角波中我们需要另加一个反馈控制信号，这个信号是通过wave的2个值合成的，flag生效范围是当wave_choise=2时，观察波形发现，wave最小值为1（不是0），因此要用wave=1控制flag的0-1翻转，而1-0翻转的控制信号仍为wave=19