题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

    reg [5:0] reg_a;
    reg [2:0] cnt;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            reg_a <= 6'b0; // Reset the register
            cnt <= 3'b0; // Reset the counter
        end else if (valid_a) begin
            reg_a <= {data_a,reg_a[5:1]}; // Shift in the new bit 'data_a'
            if (cnt < 3'd6) begin
                cnt <= cnt + 1; // Increment the counter until it reaches 7
            end else begin
                cnt <= 3'b1; // Keep the counter at 7 after reaching it
            end
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            ready_a <= 1'b0; // Reset ready_a
        end
        else begin
            ready_a <= 1'b1; // Set ready_a to 1 when valid_a is high
        end
    end
    
    always @(*) begin
        if (!rst_n) begin
            valid_b <= 1'b0;
            data_b <= 6'b0;
        end else if (cnt == 3'd6) begin
            valid_b <= 1'b1; // Valid output when counter reaches 7
            data_b <= reg_a; // Output the current register value
        end else begin
            valid_b <= 1'b0; // No valid output yet
            data_b <= data_b; // Reset output data when not valid
        end
    end
endmodule