题解 | 可置位计数器

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
//开头从0开始的，延迟一个时钟周期+1  
always@(posedge clk or negedge rst_n)
if(!rst_n)
  number <= 0;
else
  number <= number0;

reg [3:0] number0;
always@(posedge clk or negedge rst_n)
if(!rst_n) 
  number0 <= 0;
else if(number0==4'd15)
  number0 <= 0;
else if(set) 
  number0 <= set_num;
else 
  number0 <= number0 + 1'b1;
  
always@(posedge clk or negedge rst_n)
if(!rst_n)
  zero <= 0;
else 
  zero <= (number0==0) ? 1 : 0;
endmodule