题解 | 根据状态转移图实现时序电路

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
reg [1:0] state, next_state;
always @(posedge clk or rst_n) begin
    if(~rst_n) state <= 0;
    else state <= next_state;
end
always @(*) begin
    case(state)
    2'b00: begin
        if(C) next_state = 2'b01;
        else next_state = 2'b00;
    end
    2'b01: begin
        if(C) next_state = 2'b01;
        else next_state = 2'b11;
    end
    2'b11: begin
        if(C) next_state = 2'b10;
        else next_state = 2'b11;
    end
    2'b10: begin
        if(C) next_state = 2'b10;
        else next_state = 2'b00;
    end
    endcase
end
assign Y = (state==2'b11)||(state==2'b10 && C);
endmodule