题解 | ROM的简单实现

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg [3:0] data_reg;
 always @(*) begin
       if (~rst_n) begin
			data_reg = 0;
	   end else begin
			case(addr)
			8'b0000_0000: data_reg =4'd0;
			8'b0000_0001: data_reg =4'd2;
			8'b0000_0010: data_reg =4'd4;
			8'b0000_0011: data_reg =4'd6;
			8'b0000_0100: data_reg =4'd8;
			8'b0000_0101: data_reg =4'd10;
			8'b0000_0110: data_reg =4'd12;
			8'b0000_0111: data_reg =4'd14;
			default:data_reg =4'd0;
			endcase
	   end
	end

assign data = data_reg;
endmodule

`timescale 1ns/1ns
module rom(
    input clk,
    input rst_n,
    input [7:0]addr,
     
    output [3:0]data
);
 
reg [3:0] rom_data [7:0];
 
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        rom_data[0]<=4'd0;
        rom_data[1]<=4'd2;
        rom_data[2]<=4'd4;
        rom_data[3]<=4'd6;
        rom_data[4]<=4'd8;
        rom_data[5]<=4'd10;
        rom_data[6]<=4'd12;
        rom_data[7]<=4'd14;
    end
    else begin
        rom_data[0]<=rom_data[0];
        rom_data[1]<=rom_data[1];
        rom_data[2]<=rom_data[2];
        rom_data[3]<=rom_data[3];
        rom_data[4]<=rom_data[4];
        rom_data[5]<=rom_data[5];
        rom_data[6]<=rom_data[6];
        rom_data[7]<=rom_data[7];
    end
end
    assign data = rom_data[addr];
endmodule