题解 | 使用8线-3线优先编码器Ⅰ实现16线-4线优先编码器

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);

wire [2:0] Y_f1,Y_f2;
wire GS_f1,EO_f1,GS_f2,EO_f2;

encoder_83 encoder_83_h8(A[15:8],EI,Y_f1,GS_f1,EO_f1);
encoder_83 encoder_83_l8(A[7 :0],EI,Y_f2,GS_f2,EO_f2);

assign L = (GS_f1)? (Y_f1 + Y_f2 + 1'b1) : Y_f2;//注意高位无输入时，采用低位解码输出；高位有输入时，需加1

assign GS = GS_f1 | GS_f2;
assign EO = EO_f1 & EO_f2;


endmodule