题解 | #输入序列不连续的序列检测#

module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output wire match
	);

    parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;
    reg [2:0] state, nsate;

    always @(posedge clk or negedge rst_n) state <= !rst_n ? s0 : nsate;

    always @(*) begin
        case(state)
            s0: nsate = data == 0 && data_valid == 1 ? s1 : s0;
            s1: nsate = data == 1 && data_valid == 1 ? s2 : s1;
            s2: nsate = data == 1 && data_valid == 1 ? s3 : s1;
            s3: nsate = data == 0 && data_valid == 1 ? s4 : s0;
            s4: nsate = data == 0 && data_valid == 1 ? s1 : s2;
            default: nsate = s0;
        endcase
    end

    // always @(posedge clk or negedge rst_n) begin
    //     if (!rst_n) begin
    //         match <= 0;
    //     end else begin
    //         match <= state == s4;
    //     end
    // end

	assign match = state == s4;

endmodule