题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);


reg Y1;
reg Q1, Q2;
reg Q1n,Q2n;
always@(posedge clk or negedge rst_n)begin 
if (!rst_n) begin
        Y1 <= 0;
        Q1 <= 0;
        Q2 <= 0;
        Q1n<=0;
        Q2n<=0;
end else begin
Q1<=Q1n;
Q2<=Q2n;
end


end

always @(*) begin
    
        case ({Q1, Q2})
            2'b00: begin 
                if (A == 0) begin
                    Q1n = 1'b0;
                    Q2n = 1'b1;
                    Y1 = 1'b0;
                end else if (A == 1) begin
                    Q1n = 1'b1;
                    Q2n = 1'b1;
                    Y1 = 1'b0;
                end
            end
            2'b01: begin 
                if (A == 0) begin
                    Q1n = 1'b1;
                    Q2n = 1'b0;
                    Y1 = 1'b0;
                end else if (A == 1) begin
                    Q1n = 1'b0;
                    Q2n = 1'b0;
                    Y1 = 1'b0;
                end
            end
            2'b10: begin 
                if (A == 0) begin
                    Q1n = 1'b1;
                    Q2n = 1'b1;
                    Y1 = 1'b0;
                end else if (A == 1) begin
                    Q1n = 1'b0;
                    Q2n = 1'b1;
                    Y1 = 1'b0;
                end
            end
            2'b11: begin 
                if (A == 0) begin
                    Q1n = 1'b0;
                    Q2n = 1'b0;
                    Y1 = 1'b1;
                end else if (A == 1) begin
                    Q1n = 1'b1;
                    Q2n = 1'b0;
                    Y1 = 1'b1;
                end
            end
            default: begin
                Q1n = 1'b0;
                Q2n = 1'b0;
                Y1 = 1'b0;
            end
        endcase
    end


// 用 assign 语句，将 Y1 的值赋给 Y
assign Y = Y1;
endmodule