题解 | #根据RTL图编写Verilog程序#
根据RTL图编写Verilog程序
https://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg Q1 ; wire always1 ; assign always1 = (Q1 & data_in) ; always@(posedge clk, negedge rst_n)begin if(!rst_n)begin Q1 <= 1'b1 ; end else begin Q1 <= ~data_in ; end end always@(posedge clk, negedge rst_n)begin if(!rst_n)begin data_out <= 1'b0 ; end else begin data_out <= always1 ; end end endmodule