题解 | #优先编码器Ⅰ#

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
    reg [2:0] Y_r;
    reg GS_r;
    reg EO_r;
    always@(*)begin
        casex({EI,I[7:0]})
        9'b0_xxxx_xxxx:{Y_r[2:0],GS_r,EO_r} = 5'b00000;
        9'b1_0000_0000:{Y_r[2:0],GS_r,EO_r} = 5'b00001;
        9'b1_1xxx_xxxx:{Y_r[2:0],GS_r,EO_r} = 5'b11110;
        9'b1_01xx_xxxx:{Y_r[2:0],GS_r,EO_r} = 5'b11010;
        9'b1_001x_xxxx:{Y_r[2:0],GS_r,EO_r} = 5'b10110;

        9'b1_0001_xxxx:{Y_r[2:0],GS_r,EO_r} = 5'b10010;
        9'b1_0000_1xxx:{Y_r[2:0],GS_r,EO_r} = 5'b01110;
        9'b1_0000_01xx:{Y_r[2:0],GS_r,EO_r} = 5'b01010;
        9'b1_0000_001x:{Y_r[2:0],GS_r,EO_r} = 5'b00110;
        9'b1_0000_0001:{Y_r[2:0],GS_r,EO_r} = 5'b00010;
        endcase
    end
    assign Y = Y_r;
    assign GS = GS_r;
    assign EO = EO_r;
endmodule