题解 | #含有无关项的序列检测#

`timescale 1ns/1ns

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg [8:0] r_data_latch ;

localparam P_SAQUENC1 = 3'b011 ;
localparam P_SAQUENCE2 = 3'b110 ;
wire w_msb_match;
wire w_lsb_match;
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		r_data_latch <= 9'bzzzzzzzz ;
	else
		r_data_latch <= {r_data_latch[7:0],a};
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match <= 0;
	else if(w_msb_match && w_lsb_match)
		match <= 1;
	else 
		match <= 0;

assign w_msb_match = r_data_latch[8:6] == P_SAQUENC1 ;
assign w_lsb_match = r_data_latch[2:0] == P_SAQUENCE2 ;

endmodule