题解 | #输入序列连续的序列检测#

// `timescale 1ns/1ns
// module sequence_detect(
// 	input clk,
// 	input rst_n,
// 	input a,
// 	output reg match
// 	);
//  reg [7:0] a_tem;
     
//     always @(posedge clk or negedge rst_n)
//         if (!rst_n)
//             begin 
//                 match <= 1'b0; a_tem <= 8'b0;
//             end
//         else if (a_tem == 8'b01110001)
//             begin
//                 match <= 1'b1;a_tem <= {a_tem[6:0],a};
//             end
//         else 
//             begin  
//                 match <= 1'b0;a_tem <= {a_tem[6:0],a};
//             end 
// endmodule

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    
    reg [4:0] state,next_state;
    parameter IDLE = 4'd0,
    S1 = 4'd1,S2 = 4'd2,
    S3 = 4'd3,S4 = 4'd4,
    S5 = 4'd5,S6 = 4'd6,
    S7 = 4'd7,S8 = 4'd8;
    
    //第一段用同步时序逻辑来描述状态的变化
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            state <= IDLE;
        else
            state <= next_state;
    
    //第二段用组合逻辑来描述状态变化的条件
    always@(*)
        begin
            next_state = IDLE;
            
            case(state)
                IDLE:next_state = a?IDLE:S1;
                S1:next_state = a?S2:S1;
                S2:next_state = a?S3:S1;
                S3:next_state = a?S4:S1;
                S4:next_state = a?IDLE:S5;
                S5:next_state = a?S2:S6;
                S6:next_state = a?S2:S7;
                S7:next_state = a?S8:S1;
                S8:next_state = a?IDLE:S1;                
            endcase
            
        end
    
  //第三段用时序逻辑来表达输出
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            match <= 1'd0;
    else if(state == S8)
            match <= 1'd1;
        else
            match <= 1'd0;

  
endmodule