题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

reg pulse;
reg [2:0] data_in_reg;

always @(posedge clk_fast or negedge rst_n)begin
	if(!rst_n)begin
		pulse <= 1'b0;
	end
	else begin
		pulse <= data_in ? ~pulse : pulse;
	end
end

always @(posedge clk_slow or negedge rst_n)begin
	if(!rst_n)begin		
		data_in_reg <= 3'b000;
	end
	else begin
		data_in_reg <= {data_in_reg[1:0] , pulse};
	end
end

assign dataout = data_in_reg[2] ^ data_in_reg[1];

endmodule