题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);

reg [3:0] ram1[7:0];

always @(posedge clk or negedge rst_n)begin
	if(write_en)begin
		ram1[write_addr] <= write_data;
	end
	else begin
		ram1[write_addr] <= 4'b0000;
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		read_data <= 4'b0000;
		ram1[0] <= 4'b0000;
		ram1[1] <= 4'b0000;
		ram1[2] <= 4'b0000;
		ram1[3] <= 4'b0000;
		ram1[4] <= 4'b0000;
		ram1[5] <= 4'b0000;
		ram1[6] <= 4'b0000;
		ram1[7] <= 4'b0000;
	end
	else begin
		if(read_en)begin
			read_data <= ram1[read_addr];
		end
		else begin
			read_data <= read_data;
		end
	end
end
	
endmodule