题解 | #RAM的简单实现#

//可综合; integer 不可综合
`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	
reg [3 :0] ram[7 :0]    ;

//write
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        ram[0]  <= 4'd0 ;
        ram[1]  <= 4'd0 ;
        ram[2]  <= 4'd0 ;
        ram[3]  <= 4'd0 ;
        ram[4]  <= 4'd0 ;
        ram[5]  <= 4'd0 ;
        ram[6]  <= 4'd0 ;
        ram[7]  <= 4'd0 ;
    end
    else if(write_en) 
    begin
        case (write_addr)
            4'd0: ram[0]  <= write_data ;
            4'd1: ram[1]  <= write_data ;
            4'd2: ram[2]  <= write_data ;
            4'd3: ram[3]  <= write_data ;
            4'd4: ram[4]  <= write_data ;
            4'd5: ram[5]  <= write_data ;
            4'd6: ram[6]  <= write_data ;
            4'd7: ram[7]  <= write_data ;
            default: ;
        endcase
    end
end

//read
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        read_data <= 4'd0    ;
    else if(read_en)
    begin
        case(read_addr)
            4'd0: read_data <= ram[0]   ;
            4'd1: read_data <= ram[1]   ;
            4'd2: read_data <= ram[2]   ;
            4'd3: read_data <= ram[3]   ;
            4'd4: read_data <= ram[4]   ;
            4'd5: read_data <= ram[5]   ;
            4'd6: read_data <= ram[6]   ;
            4'd7: read_data <= ram[7]   ;
            default: ;
        endcase
    end
end











endmodule