题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
reg [3:0] ram1[127:0];
reg [3:0] r_data_reg;
assign r_data = r_data_reg;

always @(negedge clk or negedge rst)begin
    if(!rst)begin
        r_data_reg <= 4'b0000;
        ram1[0] <= 4'b0000;
    end
    else begin
        if(enb)begin
            ram1[addr] <= w_data;
        end
        else begin
            r_data_reg <= ram1[addr];
        end
    end
end


//*************code***********//
endmodule