题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns

module min(
	input clk,
	input rst_n,
	input [7:0]data_a,
	input [7:0]data_b,
	
	output [7:0]data_d
);

reg [7:0]data_d_reg;
wire[7:0]data_min;
assign data_d = data_d_reg;
assign data_min = (data_a >= data_b)?data_b:data_a;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_d_reg <= 8'b00000000;
	end
	else begin
		data_d_reg <= data_min;
	end
end

endmodule

module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire [7:0]out1;
wire [7:0]out2;
wire [7:0]out3;

min u1(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(a),
	.data_b(b),
	.data_d(out1)
);

min u2(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(a),
	.data_b(c),
	.data_d(out2)
);

min u3(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(out1),
	.data_b(out2),
	.data_d(out3)
);

assign d = out3;

endmodule