题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

parameter IDLE      = 5'b00001;
parameter S1        = 5'b00010;
parameter S2        = 5'b00100;
parameter S3        = 5'b01000;
parameter S4        = 5'b10000;

//REG DEFINED
reg     [4:0]       curr_state;
reg     [4:0]       next_state;

//fsm
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        curr_state <= IDLE;
    end
    else
        curr_state <= next_state;
end

always @( *) begin
    if (data_valid) begin
        case (curr_state)
            IDLE:if (!data) 
            next_state = S1;
            else
            next_state = IDLE;
            S1:if (data) 
            next_state = S2;
            else
            next_state = S1;
            S2:if (data) 
            next_state = S3;
            else
            next_state = S1;
            S3:if (!data) 
            next_state = S4;
            else
            next_state = IDLE;
            S4:if (!data) 
            next_state = S1;
            else
            next_state = IDLE;
            default : next_state = curr_state;
        endcase
    end
    else begin
        next_state = curr_state;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        match <= 1'b0;
    end
    else
        if (next_state == S4 && data_valid && !data) begin
            match <= 1'b1;
        end
        else
            match <= 1'b0;
end
endmodule