题解 | #全加器#

全加器，例化三次半加器

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire s_half, c_half;
wire s_half_1, c_half_1, s_half_2;

add_half add_full_inst1(
    .A(A),
    .B(B),

    .S(s_half),
    .C(c_half)
);

add_half add_full_inst2(
    .A(s_half),
    .B(Ci),

    .S(S),
    .C(c_half_1)
);

add_half add_full_inst3(
    .A(c_half),
    .B(c_half_1),

    .S(Co),
    .C()
);

endmodule