题解 | #时钟切换#

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//
	reg sel0,sel1;

	always @(negedge clk0 or negedge rst) begin
		if(~rst) begin
			sel0 <= 1'b0;
		end
		else begin
			sel0 <= (~sel) & (~sel1);
		end
	end

	always @(negedge clk1 or negedge rst) begin
		if(~rst) begin
			sel1 <= 1'b0;
		end
		else begin
			sel1 <= (sel) & (~sel0);
		end
	end

	always @(*) begin
		clk_out = (sel0 & clk0) | (sel1 & clk1);
	end

//*************code***********//
endmodule

观察到题给波形下降沿是同步的，所以可以分别在两个时钟的下降沿进行时钟切换。