题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output  reg match
	);

reg [4:0] cs;
reg [4:0] ns;

parameter   IDLE = 5'b0_0001,
              S0 = 5'b0_0010,
              S1 = 5'b0_0100,
              S2 = 5'b0_1000,
              S3 = 5'b1_0000;

//1st
always @ (posedge clk or negedge rst_n)
begin
	if (~rst_n)
	    cs <= IDLE;
	else 
		cs <= ns;   
end	

//2nd
always @ (*)
begin
	if (data_valid == 1'b1) begin   //data_valid有效时输入data才有效，不建议把data_valid放在1st中
	case(cs)
	IDLE: ns = (data == 1'b0) ? S0 : IDLE;
	S0:   ns = (data == 1'b1) ? S1 : S0;
	S1:   ns = (data == 1'b1) ? S2 : S0;
	S2:   ns = (data == 1'b0) ? S3 : IDLE;
	S3:   ns = (data == 1'b0) ? S0 : IDLE;
	default: ns = IDLE;
	endcase
	end
	else 
	ns = ns;
end

//3rd
always @ (posedge clk or negedge rst_n)
begin
	if (~rst_n)
	    match <= 1'b0;
	else begin
		if (ns == S3) 
		   match <= 1'b1; 
		else
		   match <= 1'b0;
	end   
end	


//assign match = (cs == S3);  如果用assign,match要改成wire型


endmodule