题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
wire clk, rst;
wire [15:0] d;
wire [1:0] sel;
reg  [15:0] d_dly;
reg  [4:0] out;
reg  validout;
//wire [3:0] d0, d1, d2, d3;
wire [4:0] out1, out2, out3;
assign out1 = d_dly[3:0] + d_dly[7:4];
assign out2 = d_dly[3:0] + d_dly[11:8];
assign out3 = d_dly[3:0] + d_dly[15:12];

always @(posedge clk or negedge rst) begin 
    if(!rst) begin 
        d_dly <= 16'd0;
        out   <= 5'd0;
        validout <= 1'd0;
    end
    else if(sel==2'd0) begin
        validout <= 1'd0;
        d_dly    <= d; 
        out      <= 16'd0;
    end
    else if(sel==2'd1) begin
        validout <= 1'd1;
        out      <= out1; 
    end
    else if(sel==2'd2) begin
        validout <= 1'd1;
        out      <= out2; 
    end
    else if(sel==2'd3) begin
        validout <= 1'd1;
        out      <= out3; 
    end

end

//*************code***********//
endmodule