题解 | #Johnson Counter#

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output     [3:0]     Q  
);

reg [7:0] jorson_cnt_reg;

always @( posedge clk or negedge rst_n )
begin
    if( !rst_n )
        jorson_cnt_reg <= 8'hf0;
    else
        jorson_cnt_reg <= {jorson_cnt_reg[0], jorson_cnt_reg[7:1]};
end

assign Q = jorson_cnt_reg[3:0];

endmodule