题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg   		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [4:0] data_reg;

localparam BIT1 = 3'd0;
localparam BIT2 = 3'd1;
localparam BIT3 = 3'd2;
localparam BIT4 = 3'd3;
localparam BIT5 = 3'd4;
localparam BIT6 = 3'd5;
reg [2:0] state;

always @( posedge clk or negedge rst_n )
begin
	if( !rst_n )
	begin
		ready_a  <= 1'b0;
		data_reg <= 5'd0;
		data_b   <= 6'd0;
		valid_b  <= 1'b0;
		state    <= BIT1;
	end
	else
	begin
		ready_a <= 1'b1;
		case( state )
		BIT1:
		begin
			valid_b <= 1'b0;
			data_b  <= data_b;
			if( valid_a )
			begin
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT2;
			end
			else
			begin
				data_reg <= data_reg;
				state    <= BIT1;
			end
		end
		BIT2:
		begin
			valid_b <= 1'b0;
			data_b  <= data_b;
			if( valid_a )
			begin
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT3;
			end
			else
			begin
				data_reg <= data_reg;
				state    <= BIT2;
			end
		end
		BIT3:
		begin
			valid_b <= 1'b0;
			data_b  <= data_b;
			if( valid_a )
			begin
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT4;
			end
			else
			begin
				data_reg <= data_reg;
				state    <= BIT3;
			end
		end
		BIT4:
		begin
			valid_b <= 1'b0;
			data_b  <= data_b;
			if( valid_a )
			begin
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT5;
			end
			else
			begin
				data_reg <= data_reg;
				state    <= BIT4;
			end
		end
		BIT5:
		begin
			valid_b <= 1'b0;
			data_b  <= data_b;
			if( valid_a )
			begin
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT6;
			end
			else
			begin
				data_reg <= data_reg;
				state    <= BIT5;
			end
		end
		BIT6:
		begin
			if( valid_a )
			begin
				valid_b  <= 1'b1;
				data_b   <= {data_a, data_reg};
				data_reg <= {data_a, data_reg[4:1]};
				state    <= BIT1;
			end
			else
			begin
				valid_b  <= 1'b0;
				data_b   <= 6'd0;
				data_reg <= data_reg;
				state    <= BIT6;
			end
		end
		endcase
	end
end

endmodule