题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [4:0] cnt;
reg clk_r;
always @(posedge clk_in or negedge clk_in or negedge rst)
if (!rst)
cnt<=0;
else
cnt<=(cnt==6)?0:cnt+1;

always @(posedge clk_in or negedge clk_in or negedge rst)
if (!rst)
clk_r<=0;
else if (cnt==6)
clk_r<=~clk_r;

assign clk_out7=clk_r;

//*************code***********//
endmodule