题解 | #自动贩售机2#

自动贩售机2

https://www.nowcoder.com/practice/298dec1c3dce45c881f3e53e02558828

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
parameter s0=8'b00000001,
		  s1=8'b00000010,
		  s2=8'b00000100,
		  s3=8'b00001000,
		  s4=8'b00010000,
		  s5=8'b00100000,
		  s6=8'b01000000;


		  reg [7:0]n_state;
		  reg [7:0]c_state;

		  wire [2:0]reg_d;
		  assign reg_d={sel,d1,d2};

		always@(posedge clk or negedge rst)
		if(!rst)
			c_state<=s0;
		else
			c_state<=n_state;

		always@(*) 
		case(c_state)
		s0:begin
			if(reg_d[1:0]==2'b10)
				n_state=s1;
			else if(reg_d[1:0]==2'b01)	
				n_state=s2;
		end 
		s1:begin
			if(reg_d[1:0]==2'b10)
				n_state=s2;
			else if(reg_d[1:0]==2'b01)	
				n_state=s3;
		end
		s2:begin
			if(reg_d[1:0]==2'b10)
				n_state=s3;
			else if(reg_d[1:0]==2'b01)	
				n_state=s4;
		end
		s3:begin
			if(reg_d[2]==0)
				n_state=s0;	
			else if(reg_d[1:0]==2'b10)
				n_state=s4;
			else if(reg_d[1:0]==2'b01)
				n_state=s5;
			else	
				n_state=n_state;
		end
		s4:begin
			if(reg_d[2]==0)
				n_state=s0;	
			else if(reg_d[1:0]==2'b10)
				n_state=s5;
			else if(reg_d[1:0]==2'b01)
				n_state=s6;
			else	
				n_state=n_state;
		end
		s5:begin
			n_state=s0;	
		end
		s6:begin
			n_state=s0;
		end
		default:n_state=s0;
		endcase
		
		always@(posedge clk or negedge rst)
		if(!rst)begin
			out1<=0;
			out2<=0;
			out3<=0;
		end
		else begin
			case(n_state)
			s3:begin
				if(reg_d[2]==0)begin
					out1<=1;
					out2<=0;
					out3<=0;
				end
				else begin
					out1<=0;
					out2<=0;
					out3<=0;		
				end

			end
			s4:begin
				if(reg_d[2]==0)begin
					out1<=1;
					out2<=0;
					out3<=1;
				end
				else begin
					out1<=0;
					out2<=0;
					out3<=0;		
				end	
			end
			s5:begin
				if(reg_d[2]==1)begin
					out1<=0;
					out2<=1;
					out3<=0;
				end
				else begin
					out1<=0;
					out2<=0;
					out3<=0;		
				end		
			end
			s6:begin
				if(reg_d[2]==1)begin
					out1<=0;
					out2<=1;
					out3<=1;
				end
				else begin
					out1<=0;
					out2<=0;
					out3<=0;		
				end		
			end
			default:begin
				out1<=0;
				out2<=0;
				out3<=0;
			end
			endcase	
		end


//*************code***********//
endmodule

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ros275229:社团删了吧,cf因该1200才勉强入门吧,也删了,你可以写算法刷了多少道,都比这个好
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