题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

	reg [2:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			cnt <= 0;
		end else begin
			if (ready_a && valid_a) begin
				if (cnt == 3) begin
					cnt <= 0;
				end else begin
					cnt <= cnt + 1;
				end
			end
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			valid_b <= 0;
		end else begin
			case (valid_b)
				1'b0: begin
					if (ready_a && valid_a && cnt == 3) begin
						valid_b <= 1'b1;
					end else begin
						valid_b <= valid_b;
					end
				end
				1'b1: begin
					if (ready_b) begin
						valid_b <= 1'b0;
					end else begin
						valid_b <= valid_b;
					end
				end
				default: begin
					valid_b <= 0;
				end
			endcase
		end
	end

	assign ready_a = ~(valid_b & ~ready_b);

	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			data_out <= 0;
		end else begin
			if (valid_a && ready_a) begin
				if (cnt == 0) begin
					data_out <= data_in;
				end else begin
					data_out <= data_out + data_in;
				end
			end else begin
				data_out <= data_out;
			end
		end
	end


endmodule

ready_a 只在 valid_b 为 1 且 ready_b 为 0 时置 0。