题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
// assign mux_out = (sel[0])? ((sel[1])?d0:d2):((sel[1]?d1:d3));
    reg [1:0]    out;
    always@(*)
        begin
            case(sel)
                2'b00 : out = d3;
                2'b01 : out = d2;
                2'b10 : out = d1;
                2'b11 : out = d0;
                default : out = d0;
            endcase
        end
    assign mux_out = out;

//*************code***********//
endmodule