题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

	and (g0, A_in[0], B_in[0]);
	and (g1, A_in[1], B_in[1]);
	and (g2, A_in[2], B_in[2]);
	and (g3, A_in[3], B_in[3]);

	xor (p0, A_in[0], B_in[0]);
	xor (p1, A_in[1], B_in[1]);
	xor (p2, A_in[2], B_in[2]);
	xor (p3, A_in[3], B_in[3]);

	xor (S[0], p0, C_1);
	xor (S[1], p1, c0);
	xor (S[2], p2, c1);
	xor (S[3], p3, c2);

	and (pc0, p0, C_1);
	and (pc1, p1, c0);
	and (pc2, p2, c1);
	and (pc3, p3, c2);

	or (c0, g0, pc0);
	or (c1, g1, pc1);
	or (c2, g2, pc2);
	or (CO, g3, pc3);


	
    
endmodule