题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

    reg [2:0] cnt; 
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            cnt <= 0;
        end else begin
            if (cnt == 3) begin
                cnt <= 0; 
            end else begin
                cnt <= cnt + 1;
            end
        end
    end

    reg [7:0] d_reg;
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            d_reg <= 0;
            input_grant <= 0;
            out <= 0;
        end else begin
            case (cnt) 
                3'd0: begin
                    input_grant <= 1;
                    out <= d;
                    d_reg <= d;
                end
                3'd1: begin
                    input_grant <= 0;
                    out <= d_reg * 3;
                end
                3'd2: begin
                    input_grant <= 0;
                    out <= d_reg * 7;
                end
                3'd3: begin
                    input_grant <= 0;
                    out <= d_reg * 8;
                end
            endcase
        end
    end

//*************code***********//
endmodule

采用计数器作为状态机，在计数0时保存输入数据，输入有效置1，并输出该数据；计数1,2,3时分别输出保存数据的3,7,8倍。